A novel single-phase multi-level inverter topology based on bridge-type connected sources with enhanced number of levels per number of devices

Document Type : Original Article

Authors

Sahand University of Technology

Abstract

This paper proposes a developed basic Multi-Level Inverter that is commercially suited for higher number of levels. The suggested topology can produce larger ratios of steps per DC sources, switches, gate-driver circuits and total devices than previous structures. The increased levels of suggested topology has led to low THD and better power quality. Accordingly, the output-side filter can be removed or its size can be reduced. The proposed topology doesn’t employ H-bridge to produce negative levels. So, the total voltage stress on switches is reduced in great extent. All the aforementioned properties make the suggested topology a compact, light and cheaper structure. Also, the suitability for supplying resistive-inductive (R-L) loads is another merit of suggested topology. Since the magnitude of DC sources influences the number of levels, three different scenarios have been considered for selecting magnitude of DC sources in basic topology. Then, the switching states, key parameters and blocking voltage on switches of suggested basic topology have been presented for each scenario. In the following, the generalized topology have been proposed that is consisted of cascaded basic units. Then, a generalized methodology has been suggested for selecting magnitude of DC sources in generalized topology to minimize redundant switching states and maximize number of voltage levels. To verify properties of suggested topology, it has been compared with similar novel structures. Also, to check correct performance of suggested topology, its basic version has been simulated in PSCAD/EMTDC software. The comparison and simulation outcomes certify advantages and correct operation of proposed topology.

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References

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Journal of Energy Management and Technology
Volume 4, Issue 3
Summer 2020
Pages 37-47

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History

  • Receive Date: 12 October 2019
  • Revise Date: 24 January 2020
  • Accept Date: 01 April 2020

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